1. Field of the Invention
The present invention relates to a programmable logic array (PLA) circuit and more particularly to a PLA circuit suitable for control circuits such as microcomputers, microprocessors and digital signal processors.
2. Description of Prior Art
A programmable logic array is a general-purpose logic structure consisting of an array of logic circuits. The way in which these circuits are programmed determines how input signals to the PLA are processed. For example, the PLA can be incorporated in a one-chip microcomputer to decode instructions and to produce control signals to various internal circuits.
A PLA circuit is disclosed in Japanese Patent Publication, (KOKAI) No. 59-100627 (Reference 1) and (KOKAI) No. 60-223326 (Reference 2.)
Reference 1 discloses a dynamic PLA circuit that includes at least two serially connected transistor groups and that performs a pre-charging/pull-down operation in synchronism with a clock signal. In each of the transistor groups, transistors have the conductive paths passes connected in parallel and control gates each connected to a data input line of each row. These transistor groups have a node which is prechargable during operation. An AND arithemetic result is output from one end of the serially connected transistor groups when the other end of the transistor groups is pulled-down, at least, to a low voltage at prescribed intervals during operation.
Reference 2 discloses a PLA circuit in a partial dynamic structure which is constructed with an AND-OR plane. In the PLA circuit, an output from the AND plane is input during precharge of the OR plane and then an output from the OR plane is read out as a PLA output during precharge of the AND plane. In this manner, the circuit is structurally simplified by precharging alternately the OR and AND planes.
However, the prior art PLA circuit has the following disadvantages.
The PLA circuit in reference 1 has a disadvantage in that an PLA output cannot be obtained during its precharge duration.
The PLA circuit in reference 2 cannot provide a PLA output during the precharge of the OR plane. This means that the prior art PLA circuits cannot utilize, effectively and arbitrarily, PLA output during the entire precharging period. This shortcoming lowers the speed of a control circuit with the PLA circuit and results in both low operational speed of instructions and low throughputs.